1. Field of the Invention
The invention relates to a method for making hemi-spherical grains on the surface of a semiconductor chip, and more specifically, to a method for enlarging surface area of a plurality of hemi-spherical grains on the surface of a semiconductor chip.
2. Description of the Prior Art
To improve the function of a capacitor which occupys a very small volume on the surface of a semiconductor chip, the stored electric charge and cell capacitance of the capacitor can be increased by enlarging the surface area of its storage node. The storage node of a capacitor generally has a curved stack. And hemi-spherical grain (HSG) structure is extensively utilized in dynamic random access memory (DRAM) or stack DRAM to enlarge surface area of the storage node of the capacitor.
Please refer to FIG. 1 to FIG. 3. FIG. 1 to FIG. 3 show the prior art method for making HSG. As shown in FIG. 1, silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6) is heated and decomposed by performing low pressure chemical vapor deposition at 500 to 550.degree. C. An amorphous silicon layer 14 with light phosphorus dopant is then evenly deposited onto the surface of the starting substrate 12 of the semiconductor chip 10 by adding phosphine (PH.sub.3). The particles in the amorphous silicon layer 14 are removed by using SC-1 standard cleaning solution, and then the native oxide layer formed on the surface of amorphous silicon layer 14 is stripped off by using 1% hydrofluoric acid (HF). The semiconductor chip 10 is then placed into an ultra high vacuum chamber at 550 to 650.degree. C. and gaseous disilane (Si.sub.2 H.sub.6) is added into the chamber. The disilane seeding is deposited into the upper surface of the amorphous silicon layer 14, and this is used as a crystallization seed or nucleus (as shown in FIG. 2). Then, an annealing process is performed to transform the impregnated amorphous silicon layer 14 into a poly-silicon layer 16 with hemi-spherical grains (as shown in FIG. 3).
Before a dielectric film is deposited, a pre-cleaning step is performed. The surface of the semiconductor chip 10 is cleaned with SC-1 standard cleaning solution and 1% hydrofluoric acid (HF). After the pre-cleaning step is complete, a depositing process is performed where a capacitor having an HSG silicon layer is produced.
Please refer to FIG. 4. FIG. 4 is a perspective diagram of a semiconductor chip 30 having an HSG silicon layer. The semiconductor chip 30 comprises a silicon substrate 32, a diffusion region 34, two word lines 36, a planarized insulation layer 38, a storage node 40, a cell dielectric layer 42, and a field plate 44. The storage node 40 is formed by the method shown in FIG. 1 to FIG. 3. First, an amorphous silicon layer is deposited then filled with disilane seeding. An annealing process is then performed to form a poly-silicon layer having the HSG structure. This is the storage node of the capacitor.